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Cores supported by MaayanIP

Networking, Communications, Connectivity

1

USB 1.1 Phy

Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface.

2

USB 1.1 Device IP Core

USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external micro-controller necessary.

3

USB 2.0 Device IP Core

This is a USB 2.0 compliant core. USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core. A industry standard PHY interface for USB has been developed. This interface is called USB Transceiver Macrocell Interface or UTMI for short. The host interface of the USB core will be WISHBONE SoC compliant.

4

Asynchronous Serial IO Controller

Simple asynchronous serial controller (aka UART). Includes 4 byte receive and a 4 byte transmit FIFO (FIFO size can be easily adjusted). External baud rate generator (included). Very small.

5

Single Slot PCM Controller

Simple PCM Interface. Allows interface to such popular devices like TI DSPs (via McBSP bus) in PCM mode. Of course many more applications. Very small and simple core.

6

AC97 Controller IP Core

This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output.

7

I2C Master Controller

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol.

8

ATA/ATAPI Host Controller

ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface. The ATA interface provides a simple interface to (low cost) non-volatile memories, like hard disk drives, DVD players, CD(ROM) players/writers and Compact Flash and PC-CARD devices.

9

Motorola DragonBall/68K to Wishbone Bridge

This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full-featured 16bit Wishbone master bus.

10

Enhanced Motorola MC68HC11 SPI IP Core

Enhanced version of the Serial Peripheral Interface available on Motorola's MC68HC11 family of CPUs. Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation.
As with the SPI found in MC68HC11 processors the core features programmable clock phase (CPHA) and clock polarity (CPOL). The core features an 8bit wishbone interface.
Very simple, very small.

CPU, DSP, uControllers, etc

1

Mini-Risc CPU/Microcontroller (PIC Clone) IP Core

This is a Mini-RISC CPU/MicroController that is compatible with the PIC 16C57 from Microchip.

2

Open 54x DSP clone

The OpenCores54x (OC54x) DSP core is a clean room implementation of a popular family of DSPs designed by the No.1 DSP supplier from the southern part of the US.

Encryption / Decryption

1

DES IP Core

Simple DES/Triple-DES core

2

Triple DES

Simple DES/Triple-DES core  

3

AES (Rijndael) IP Core

Simple AES (Rijndael) IP Core.  

Math / Arithmetic Cores

1

Single Precision FPU (IEEE-754 compliant) IP Core

This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions. It supports four rounding modes: Round to Nearest Even, Round to Zero, Round to +INF and Round to -INF.

2

CORDIC Core

The CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.

3

Hardware Dividers 

This is a collection of synthesizeable hardware dividers. Different types of dividers are available. All dividers are fully pipelined and provide a 2N by N division every clock cycle. All designs are fully parameteriseable and synthesizeable.

The dividers take two inputs Z(2N-bit divident) and D(N-bit divisor), and return Q(N-bit quotient), S(N-bit remainder), div0(division by zero), and ovf(overflow). 

Misc. Building Blocks

1

Generic FIFOs

Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS

2

DMA/Bridge IP Core

This is a simple DMA/Bridge IP core. It has two WISHBONE interfaces. It can perform DMA transfers between the two interfaces or on the same interfaces.

3

WISHBONE Interconnect Matrix

This is a WISHBONE Interconnect Matrix IP core. It can interconnect up to 8 Masters and 16 Slaves

4

Simple General Purpose IO  

Simple General Purpose IO port. It supports up to 8 GPIO pins. Each pin is individually programmable as either input or output. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported, by using multiple instances (e.g. 4 simple GPIO cores provide a 32bit wishbone interface).

5

Simple Programmable Interrupt Controller 

Simple programmable interrupt controller. It supports up to 8 interrupt sources. Polarity and sensitivity (either edge or level) is programmable per interrupt source. The core features an 8bit wishbone interface. Wider wishbone interfaces are easily supported, by using multiple instances.  

Memory Controllers, Interfaces

1

Advanced Memory Controller IP Core

This is a advanced Memory Controller intended for embedded applications

2

SSRAM Interface

The 'SSRAM interface core' is a collection of designs for easy integration of synchronous srams (ZBT srams) in your designs

Video (CRT, LCD) Controllers, Interfaces, etc.

1

VGA/LCD Controller

The OpenCores VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost all available LCD and CRT displays

2

Video Compression System

The 'Video Compression Systems Project' was started with the idea to provide readily available blocks for compression systems. Which, combined together, form a complete compression standard.

Examples of popular standards are:

• MPEG (MPEG-1, MPEG-2, MPEG-4)
• H.310, H.320 etc. (video conferencing)
• JPEG & MJPEG
• etc.

All aspects of a standard are covered. The links on the top of this page provide access to the blocks needed to build a complete system.

3

8x8 DCT, fully pipelined  

4

QNR, Quantization  

5

Huffman Encoder  

6

Huffman Decoder  

Commercial IP

AMBA AHB - WISHBONE Wrapper IP Core

This IP Core consists of a AMBA AHB to WISHBONE and a WISHBONE to AMBA AHB interface 'wrappers'.

It is fully AMBA 2.0 and WISHBONE Rev B3 compliant.

16 Bit RISC DSP Soft IP Core

A 16 bit true RISC Architecture Digital Signal Processor for embedded applications that require high performance in a small form factor with ultra low power consumption.

16 Bit RISC MCU Soft IP Core

A 16 bit true RISC Architecture Microcontroller for embedded applications that require high performance in a small form factor with ultra low power consumption.

Enhanced AES (Rijndael) IP Core

FIPS-197 Compliant. Encrypt and decrypt modules with 128, 192 and 256 bit keys. Various versions are available, from small area to high performance, up to 34Gbit/sec in 0.18u.

Enhanced Floating Point Unit

Fully IEEE 754 Compliant.

Parameterizable Architecture:

• Single Precision (32 bit)
• Extended Single Precision (44 bit)
• Double Precision (64 bit)
• Extended Double Precision (80 bit)
• Any other user selected format

USB 2.0 On-The-Go IP Core

A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB device. This USB IP Core supports both High Speed and Full Speed transfers and automatic line speed negotiation.

Fully USB 2.0 and USB 2.0 OTG Supplement Compliant.

Features Include:

• True Dual-Role capability
• OTG high performance host mode
• Full USB peripheral capability
• Session request protocol support
• Host negotiation protocol support
• High Speed and Full Speed mode support
• Up to 16 endpoints
• Bulk, interrupt and isochronous transfers
• Slave and Master WISHBONE i/f (AMBA wrappers available)
• No dedicated local memory required
• Compact and cost-effective solution for SoC

Serial ATA Host IP Core

The Serial ATA Link and Transport Layer Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.

• 10 bit Phy interface
• Connects to SAPIS compliant serial ATA Phy
• Fully compliant to SATA Gen 1 (1.2 Gb/s) and Gen 2 (2.4 Gb/s)
• Wishbone slave interface for register access and FIFO/DMA data transfers
• 128 byte (32 double word) data FIFO (optional 256 byte)
• Implements the shadow register block and the serial ATA status and control registers
• Parallel ATA legacy software compatibility
• 48-bit address feature set supported
• Master only emulation (supports 1 device)
• CONT and data scramblers to reduce EMI
• Auto inserted HOLD primitives
• Power management support (partial and slumber)
• Optional native mode programming model
• Many configuration options

USB 1.1 Host IP Core

The USB host controller enables the use of USB peripherals in your application. The core allows the embedded processor to interface to the multitude of USB devices available, such as keyboards, external drives, cameras, wireless networking devices, etc.

• USB v1.1 and OpenHCI v1.0a compliant
• Full speed and low speed support
• Control, interrupt, bulk and isochronous transfers
• Integrated DPLL and PHY
• Root hub, supporting up to eight ports
• Port state machines enabling dynamic attachment & removal, reset, suspend and remote wakeup
• Flexible port power switching control and over current monitoring
• Master and slave Wishbone interfaces